diff options
author | 2009-10-01 22:20:47 +0400 | |
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committer | 2009-10-01 22:45:02 +0400 | |
commit | 99a0949b720a0936da2052cb9a46db04ffc6db29 (patch) | |
tree | f9e39633853e35b49fc4465337cc196b9650866e /target-mips | |
parent | Include microblaze binaries in tarbin. (diff) | |
download | qemu-kvm-99a0949b720a0936da2052cb9a46db04ffc6db29.tar.gz qemu-kvm-99a0949b720a0936da2052cb9a46db04ffc6db29.tar.bz2 qemu-kvm-99a0949b720a0936da2052cb9a46db04ffc6db29.zip |
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.
Signed-off-by: malc <av1474@comtv.ru>
Diffstat (limited to 'target-mips')
-rw-r--r-- | target-mips/cpu.h | 17 | ||||
-rw-r--r-- | target-mips/helper.c | 6 | ||||
-rw-r--r-- | target-mips/op_helper.c | 8 | ||||
-rw-r--r-- | target-mips/translate.c | 4 | ||||
-rw-r--r-- | target-mips/translate_init.c | 20 |
5 files changed, 27 insertions, 28 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c27738ac4..e7d30d156 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -21,8 +21,8 @@ typedef unsigned int uint_fast16_t; struct CPUMIPSState; -typedef struct r4k_tlb_t r4k_tlb_t; -struct r4k_tlb_t { +typedef struct r4k_tlb a_r4k_tlb; +struct r4k_tlb { target_ulong VPN; uint32_t PageMask; uint_fast8_t ASID; @@ -47,13 +47,12 @@ struct CPUMIPSTLBContext { void (*helper_tlbr) (void); union { struct { - r4k_tlb_t tlb[MIPS_TLB_MAX]; + a_r4k_tlb tlb[MIPS_TLB_MAX]; } r4k; } mmu; }; -typedef union fpr_t fpr_t; -union fpr_t { +union fpr { float64 fd; /* ieee double precision */ float32 fs[2];/* ieee single precision */ uint64_t d; /* binary double fixed-point */ @@ -71,7 +70,7 @@ union fpr_t { typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; struct CPUMIPSFPUContext { /* Floating point registers */ - fpr_t fpr[32]; + union fpr fpr[32]; float_status fp_status; /* fpu implementation/revision register (fir) */ uint32_t fcr0; @@ -130,7 +129,7 @@ struct CPUMIPSMVPContext { #define CP0MVPC1_PCP1 0 }; -typedef struct mips_def_t mips_def_t; +typedef struct mips_def a_mips_def; #define MIPS_SHADOW_SET_MAX 16 #define MIPS_TC_MAX 5 @@ -458,7 +457,7 @@ struct CPUMIPSState { CPU_COMMON - const mips_def_t *cpu_model; + const a_mips_def *cpu_model; void *irq[8]; struct QEMUTimer *timer; /* Internal timer */ }; @@ -475,7 +474,7 @@ void r4k_helper_tlbp (void); void r4k_helper_tlbr (void); void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); -void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, +void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec, int unused, int size); #define cpu_init cpu_mips_init diff --git a/target-mips/helper.c b/target-mips/helper.c index 7f659ae6b..abca44483 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -69,7 +69,7 @@ int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, int i; for (i = 0; i < env->tlb->tlb_in_use; i++) { - r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; + a_r4k_tlb *tlb = &env->tlb->mmu.r4k.tlb[i]; /* 1k pages are not supported. */ target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); target_ulong tag = address & ~mask; @@ -201,7 +201,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical, } #endif -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { #if defined(CONFIG_USER_ONLY) return addr; @@ -564,7 +564,7 @@ void do_interrupt (CPUState *env) void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) { - r4k_tlb_t *tlb; + a_r4k_tlb *tlb; target_ulong addr; target_ulong end; uint8_t ASID = env->CP0_EntryHi & 0xFF; diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index d3dab33a3..17e6ed5a8 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1508,7 +1508,7 @@ static void r4k_mips_tlb_flush_extra (CPUState *env, int first) static void r4k_fill_tlb (int idx) { - r4k_tlb_t *tlb; + a_r4k_tlb *tlb; /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ tlb = &env->tlb->mmu.r4k.tlb[idx]; @@ -1554,7 +1554,7 @@ void r4k_helper_tlbwr (void) void r4k_helper_tlbp (void) { - r4k_tlb_t *tlb; + a_r4k_tlb *tlb; target_ulong mask; target_ulong tag; target_ulong VPN; @@ -1596,7 +1596,7 @@ void r4k_helper_tlbp (void) void r4k_helper_tlbr (void) { - r4k_tlb_t *tlb; + a_r4k_tlb *tlb; uint8_t ASID; int idx; @@ -1846,7 +1846,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) env = saved_env; } -void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, +void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec, int unused, int size) { if (is_exec) diff --git a/target-mips/translate.c b/target-mips/translate.c index 58f483fa0..d05fee9f1 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -8451,7 +8451,7 @@ static void fpu_dump_state(CPUState *env, FILE *f, (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \ (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \ else { \ - fpr_t tmp; \ + union fpr tmp; \ tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \ tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \ fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \ @@ -8591,7 +8591,7 @@ static void mips_tcg_init(void) CPUMIPSState *cpu_mips_init (const char *cpu_model) { CPUMIPSState *env; - const mips_def_t *def; + const a_mips_def *def; def = cpu_mips_find_by_name(cpu_model); if (!def) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index eb35dbad3..7c8519a9c 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -61,7 +61,7 @@ enum mips_mmu_types { MMU_TYPE_R8000 }; -struct mips_def_t { +struct mips_def { const char *name; int32_t CP0_PRid; int32_t CP0_Config0; @@ -94,7 +94,7 @@ struct mips_def_t { /*****************************************************************************/ /* MIPS CPU definitions */ -static const mips_def_t mips_defs[] = +static const a_mips_def mips_defs[] = { { .name = "4Kc", @@ -416,7 +416,7 @@ static const mips_def_t mips_defs[] = #endif }; -static const mips_def_t *cpu_mips_find_by_name (const char *name) +static const a_mips_def *cpu_mips_find_by_name (const char *name) { int i; @@ -439,19 +439,19 @@ void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) } #ifndef CONFIG_USER_ONLY -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void no_mmu_init (CPUMIPSState *env, const a_mips_def *def) { env->tlb->nb_tlb = 1; env->tlb->map_address = &no_mmu_map_address; } -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void fixed_mmu_init (CPUMIPSState *env, const a_mips_def *def) { env->tlb->nb_tlb = 1; env->tlb->map_address = &fixed_mmu_map_address; } -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void r4k_mmu_init (CPUMIPSState *env, const a_mips_def *def) { env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); env->tlb->map_address = &r4k_map_address; @@ -461,7 +461,7 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) env->tlb->helper_tlbr = r4k_helper_tlbr; } -static void mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void mmu_init (CPUMIPSState *env, const a_mips_def *def) { env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext)); @@ -486,7 +486,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def) } #endif /* CONFIG_USER_ONLY */ -static void fpu_init (CPUMIPSState *env, const mips_def_t *def) +static void fpu_init (CPUMIPSState *env, const a_mips_def *def) { int i; @@ -504,7 +504,7 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def) #endif } -static void mvp_init (CPUMIPSState *env, const mips_def_t *def) +static void mvp_init (CPUMIPSState *env, const a_mips_def *def) { env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext)); @@ -531,7 +531,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def) (0x1 << CP0MVPC1_PCP1); } -static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def) +static int cpu_mips_register (CPUMIPSState *env, const a_mips_def *def) { env->CP0_PRid = def->CP0_PRid; env->CP0_Config0 = def->CP0_Config0; |