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* x86: drop redundant SYSCALL/SYSRET templatesJan Beulich2019-11-143-26/+5
| | | | | | | | The Cpu64 forms are no different in their attributes except for the CPU flags; there's no need to key these off of anything other than CpuSYSCALL even for the 64-bit forms. Dropping these improves the diagnostic on SYSRETQ used in 32-bit code from "unsupported instruction `sysret'" to "invalid instruction suffix for `sysret'".
* x86: fold individual Jump* attributes into a single Jump oneJan Beulich2019-11-145-14858/+10948
| | | | ..., taking just 3 bits instead of 5. No two of them are used together.
* x86: make JumpAbsolute an insn attributeJan Beulich2019-11-146-26480/+26486
| | | | | ... instead of an operand one: There's only ever one operand here anyway.
* x86: make AnySize an insn attributeJan Beulich2019-11-145-14486/+14499
| | | | | | ... instead of an operand one. Which operand it applies to can be determined from other operand properties, but as it turns out the only place it is actually used at doesn't even need further qualification.
* RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2019-11-122-60/+66
| | | | | | | | | | | | | | | | We have to enable the f extension through -march or ELF attribute if we use the FPR in .insn directive. The behavior is same as the riscv_opcodes. 2019-11-12 Nelson Chu <nelson.chu@sifive.com> opcodes/ * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we use the floating point register (FPR). gas/ * testsuite/gas/riscv/insn.d: Add the f extension to -march option. Change-Id: I4f59d04c82673ef84c56ecd2659ad8ce164dd626
* [binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu2019-11-122-6/+18
| | | | | | | | | | | | | | | | | | | | | This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode. Previously VMOV and VMVN with cmode 1101 were not allowed. The cmode changes also required updating of the MVE conflict checking. Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV and VMVN, respectively. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with cmode 1101. (is_mve_encoding_conflict): Update cmode conflict checks for MVE_VMVN_IMM. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
* x86: fold EsSeg into IsStringJan Beulich2019-11-126-11272/+11287
| | | | | | | | | | | | | | EsSeg (a per-operand bit) is used with IsString (a per-insn attribute) only. Extend the attribute to 2 bits, thus allowing to encode - not a string insn, - string insn with neither operand requiring use of %es:, - string insn with 1st operand requiring use of %es:, - string insn with 2nd operand requiring use of %es:, which covers all possible cases, allowing to drop EsSeg. The (transient) need to comment out the OTUnused #define did uncover an oversight in the earlier OTMax -> OTNum conversion, which is being taken care of here.
* x86: eliminate ImmExt abuseJan Beulich2019-11-126-93/+197
| | | | | | | | Drop the remaining instances left in place by commit c3949f432f ("x86: limit ImmExt abuse), now that we have a way to specify specific GPRs. Take the opportunity and also introduce proper 16-bit forms of applicable SVME insns as well as 1-operand forms of CLZERO.
* x86: introduce operand type "instance"Jan Beulich2019-11-127-14199/+14252
| | | | | | | | | | | Special register "class" instances can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field. Furthermore the generalization becoming possible will allow improvements to the handling of insns accepting only individual registers as their operands.
* Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich2019-11-112-2/+7
| | | | This is just like for their umaxp/uminp and fmaxp/fminp counterparts.
* Arm64: fix build with old glibcJan Beulich2019-11-112-10/+12
| | | | | | Some old glibc versions have string.h surface "index", which some compilers then warn about if shadowed by a local variable. Re-use an existing variable instead.
* i386: Only check suffix in instruction mnemonicH.J. Lu2019-11-083-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | We should check suffix in instruction mnemonic when matching instruction. In Intel syntax, normally we check for memory operand size. But the same mnemonic with 2 different encodings can have the same memory operand size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand size in Intel syntax to distinguish them. When there is no suffix in mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic suffix. gas/ PR gas/25167 * config/tc-i386.c (match_template): Don't check instruction suffix set from operand. * testsuite/gas/i386/code16.d: New file. * testsuite/gas/i386/code16.s: Likewise. * testsuite/gas/i386/i386.exp: Run code16. * testsuite/gas/i386/x86-64-branch-4.l: Updated. opcodes/ PR gas/25167 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd. * i386-tbl.h: Regenerated.
* x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich2019-11-087-14560/+14574
| | | | This is to further shrink the operand type representation.
* x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich2019-11-087-19174/+19187
| | | | This is to further shrink the operand type representation.
* x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich2019-11-087-14001/+14015
| | | | This is to further shrink the operand type representation.
* x86: convert SReg from bitfield to enumeratorJan Beulich2019-11-087-13810/+13823
| | | | This is to further shrink the operand type representation.
* x86: introduce operand type "class"Jan Beulich2019-11-086-105/+165
| | | | | | | Many operand types, in particular the various kinds of registers, can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field.
* [gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson2019-11-073-49/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. In this last patch, the new Data Gathering Hint mnemonic is introduced. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * testsuite/gas/aarch64/dgh.s: New test. * testsuite/gas/aarch64/dgh.d: New test. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions. (aarch64_opcode_table): Add data gathering hint mnemonic. * opcodes/aarch64-dis-2.c: Account for new instruction. Is it ok for trunk? Regards, Mihail
* [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson2019-11-072-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the arm backend. The following Matrix Multiply instructions are added: vummla, vsmmla, vusmmla, vusdot, vsudot[1]. [1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (arm_ext_i8mm): New feature set. (do_vusdot): New. (do_vsudot): New. (do_vsmmla): New. (do_vummla): New. (insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics. (armv86a_ext_table): Add i8mm extension. (arm_extensions): Move bf16 extension to context sensitive table. (armv82a_ext_table, armv84a_ext_table, armv85a_ext_table): Move bf16 extension to context sensitive table. (armv86a_ext_table): Add i8mm extension. * doc/c-arm.texi: Document i8mm extension. * testsuite/gas/arm/i8mm.s: New test. * testsuite/gas/arm/i8mm.d: New test. * testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/arm.h (ARM_EXT2_I8MM): New feature macro. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions. Regression tested on arm-none-eabi. Is this ok for trunk? Regards, Mihail
* [binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson2019-11-076-462/+877
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the aarch64 backend. The following instructions are added: {s/u}mmla, usmmla, {us/su}dot, fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension. (parse_operands): Add new operand. * testsuite/gas/aarch64/i8mm.s: New test. * testsuite/gas/aarch64/i8mm.d: New test. * testsuite/gas/aarch64/f32mm.s: New test. * testsuite/gas/aarch64/f32mm.d: New test. * testsuite/gas/aarch64/f64mm.s: New test. * testsuite/gas/aarch64/f64mm.d: New test. * testsuite/gas/aarch64/sve-movprfx-mm.s: New test. * testsuite/gas/aarch64/sve-movprfx-mm.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New. (AARCH64_FEATURE_F32MM): New. (AARCH64_FEATURE_F64MM): New. (AARCH64_OPND_SVE_ADDR_RI_S4x32): New. (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for instructions that do not require special handling. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, aarch64_feature_f64mm): New feature sets. (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply instructions. (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set macros. (QL_MMLA64, OP_SVE_SBB): New qualifiers. (OP_SVE_QQQ): New qualifier. (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. (aarch64_opcode_table): Define new instructions smmla, ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod uzip{1/2}, trn{1/2}. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new S4x32 operand. * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
* [binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson2019-11-072-5/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces BFloat16 instructions to the arm backend. The following BFloat16 instructions are added: vdot, vfma{l/t}, vmmla, vfmal{t/b}, vcvt, vcvt{t/b}. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_archs): Add armv8.6-a option. (cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a. * doc/c-arm.texi (-march): New armv8.6-a arch. * config/tc-arm.c (arm_ext_bf16): New feature set. (enum neon_el_type): Add NT_bfloat value. (B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder helpers. (BAD_BF16): New message. (parse_neon_type): Add bf16 type specifier. (enum neon_type_mask): Add N_BF16 type. (type_chk_of_el_type): Account for NT_bfloat. (el_type_of_type_chk): Account for N_BF16. (neon_three_args): Split out from neon_three_same. (neon_three_same): Part split out into neon_three_args. (CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour. (do_neon_cvt_1): Account for vcvt.bf16.f32. (do_bfloat_vmla): New. (do_mve_vfma): New function to deal with the mnemonic clash between the BF16 vfmat and the MVE vfma in a VPT block with a 't'rue condition. (do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32. (do_vdot): New (do_vmmla): New (insns): Add vdot and vmmla mnemonics. (arm_extensions): Add "bf16" extension. * doc/c-arm.texi: Document "bf16" extension. * testsuite/gas/arm/attr-march-armv8_6-a.d: New test. * testsuite/gas/arm/bfloat16-bad.d: New test. * testsuite/gas/arm/bfloat16-bad.l: New test. * testsuite/gas/arm/bfloat16-bad.s: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad.d: New test. * testsuite/gas/arm/bfloat16-neon.s: New test. * testsuite/gas/arm/bfloat16-non-neon.s: New test. * testsuite/gas/arm/bfloat16-thumb-bad.d: New test. * testsuite/gas/arm/bfloat16-thumb-bad.l: New test. * testsuite/gas/arm/bfloat16-thumb.d: New test. * testsuite/gas/arm/bfloat16-vfp.d: New test. * testsuite/gas/arm/bfloat16.d: New test. * testsuite/gas/arm/bfloat16.s: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A, ARM_ARCH_V8_6A): New. * opcode/arm.h (ARM_EXT2_BF16): New feature macro. (ARM_AEXT2_V8_6A): Include above macro in definition. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with Armv8.6-A. (coprocessor_opcodes): Add bfloat16 vcvt{t,b}. (neon_opcodes): Add bfloat SIMD instructions. (print_insn_coprocessor): Add new control character %b to print condition code without checking cp_num. (print_insn_neon): Account for BFloat16 instructions that have no special top-byte handling. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
* [Patch][binutils][arm] Create a new generic coprocessor array [3/10]Matthew Malcomson2019-11-072-51/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. Some generic instructions match a large range of encoding space (e.g. stc, mcr, mrc). Currently these instructions are in the coprocessor_opcodes array, which means they are checked before many other instructions when disassembling arm and thumb32 codes. This patch moves the generic instructions into a separate array to be checked later on. This is done in order to avoid instruction conflict between the generic instructions and newer ones -- this has already been seen with MVE, and is also a problem with BFloat16. One way to avoid the conflict could be to swap the search order between coprocessor_opcodes and neon_opcodes. We avoid this since it's a larger change that may introduce extra bugs (that aren't caught by the testsuite). We have decided against searching the generic array after searching the arm specific and thumb32 specific arrays with a similar reasoning about keeping the change small. Regression tested with arm-none-linux-gnueabihf. Committed on behalf of Mihail Ionescu. opcodes/ChangeLog: 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-29 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_coprocessor, print_insn_generic_coprocessor): Create wrapper functions around the implementation of the print_insn_coprocessor control codes. (print_insn_coprocessor_1): Original print_insn_coprocessor function that now takes which array to look at as an argument. (print_insn_arm): Use both print_insn_coprocessor and print_insn_generic_coprocessor. (print_insn_thumb32): As above. Is it ok for trunk? Regards, Mihail
* [binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson2019-11-076-68/+373
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the following BFloat16 instructions to the aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b], bfcvtn2. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Special case the S_2H operand qualifier. * doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions. * testsuite/gas/aarch64/bfloat16.d: New test. * testsuite/gas/aarch64/bfloat16.s: New test. * testsuite/gas/aarch64/illegal-bfloat16.d: New test. * testsuite/gas/aarch64/illegal-bfloat16.l: New test. * testsuite/gas/aarch64/illegal-bfloat16.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros. (AARCH64_ARCH_V8_6): Include BFloat16 feature macros. (enum aarch64_opnd_qualifier): Introduce new operand qualifier AARCH64_OPND_QLF_S_2H. (enum aarch64_insn_class): Introduce new class "bfloat16". (BFLOAT16_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-opc.c (struct operand_qualifier_data): Add data for new AARCH64_OPND_QLF_S_2H qualifier. * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve, aarch64_feature_bfloat16_bfmmla4): New feature sets. (BFLOAT_SVE, BFLOAT): New feature set macros. (BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros to define BFloat16 instructions. (aarch64_opcode_table): Define new instructions bfdot, bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] bfcvtn2, bfcvt. Regression tested on aarch64-elf. Is it ok for trunk? Regards, Mihail
* [gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson2019-11-072-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. This first patch adds the Armv8.6-A flag to binutils. No instructions are behind it at the moment. Commited on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (armv8.6-a): New arch. * doc/c-aarch64.texi (armv8.6-a): Document new arch. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_6): New. (AARCH64_ARCH_V8_6): New. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (ARMV8_6): New macro. Is it ok for trunk? Regards, Mihail
* x86: support further AMD Zen2 instructionsJan Beulich2019-11-077-4080/+4160
| | | | | Both RDPRU and MCOMMIT have been publicly documented meanwhile: https://www.amd.com/system/files/TechDocs/24594.pdf.
* x86: adjust register names printed for MONITOR/MWAITJan Beulich2019-11-072-16/+20
| | | | | | | | | | As the comments (here: almost, in the opcode table: fully) correctly state - all register operands except MONITOR's address one are fixed at 32 bit size. Don't print 64-bit registers there. Also adjust x86-64-suffix.d's name such that it wouldn't be identical to x86-64-rep-suffix.d's, but instead resemble that of its sibling x86-64-suffix-intel.d.
* x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD againJan Beulich2019-11-073-4/+11
| | | | | These were mistakenly added by d241b91073 ("x86/Intel: correct MOVSD and CMPSD handling"). This addresses part of PR/gas 25167.
* x86: fold OP_Mwaitx() into OP_Mwait()Jan Beulich2019-11-052-24/+11
| | | | | There's no need to have separate functions, the difference can easily be expressed using the function arguments.
* x86: split MONITORX/MWAITX entriesJan Beulich2019-11-052-2/+21
| | | | | Both encodings do not ignore the 66/F3/F2 prefixes, so don't have the disassembler ignore them either.
* x86: consolidate disassembler enum naming a littleJan Beulich2019-11-052-75/+130
| | | | | | | The original idea looks to have been for names to be composed in the order that decoding gets done, which helps both reading and modifying the code. Switch (back) to this model for some of the affected non- vector insn enumerators.
* Fix potential array overruns when disassembling corrupt v850 binaries.Nick Clifton2019-11-042-60/+129
| | | | | | | | | | | | | | * v850-dis.c (get_v850_sreg_name): New function. Returns the name of a v850 system register. Move the v850_sreg_names array into this function. (get_v850_reg_name): Likewise for ordinary register names. (get_v850_vreg_name): Likewise for vector register names. (get_v850_cc_name): Likewise for condition codes. * get_v850_float_cc_name): Likewise for floating point condition codes. (get_v850_cacheop_name): Likewise for cache-ops. (get_v850_prefop_name): Likewise for pref-ops. (disassemble): Use the new accessor functions.
* Modify the ARNM assembler to accept the omission of the immediate argument ↵Delia Burduv2019-10-304-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for the writeback form of the LDRAA and LDRAB mnemonics This is a shorthand for the immediate argument being 0, as described here: https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication This is because the instructions still have a use with an immediate argument of 0, unlike loads without the PAC functionality. Currently, the mnemonics are LDRAA Xt, [Xn, #<simm10>]! LDRAB Xt, [Xn, #<simm10>]! After this patch they become LDRAA Xt, [Xn {, #<simm10>}]! LDRAB Xt, [Xn {, #<simm10>}]! gas * config/tc-aarch64.c (parse_address_main): Accept the omission of the immediate argument for ldraa and ldrab as a shorthand for the immediate being 0. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test. * testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the writeback form with no offset. * testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset error. opcodes * aarch64-opc.c (print_immediate_offset_address): Don't print the immediate for the writeback form of ldraa/ldrab if it is 0. * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10. * aarch64-opc-2.c: Regenerated.
* x86: re-do "shorthand" handlingJan Beulich2019-10-304-219/+214
| | | | | | | Now that the opcode table gets preprocessed, undo parts of commit dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64"): Have the preprocessor handle the expansion there, while making the expansions explicit in i386-gen and the register table.
* x86: slightly rearrange struct insn_templateJan Beulich2019-10-304-3918/+3925
| | | | | This avoids holes between the individual fields, (potentially) shrinking the overall template table size by 4 bytes per entry.
* x86: drop stray WJan Beulich2019-10-305-19/+54
| | | | | | | | | | | The flag is used to indicate opcodes which can be switched between byte and word/dword/qword forms (in a "canonical" way). Obviously it's quite odd then to see it on insns not allowing for byte operands in the first place. As a result the opcode bytes need to be adjusted accordingly, which includes comparisons done in optimize_encoding(). To make re-introduction of such issues less likely have i386-gen diagnose it (in a generally non-fatal way for now).
* Fix array overrun when disassembling corrupt TIC30 binaries.Nick Clifton2019-10-292-1/+5
| | | | * tic30-dis.c (print_branch): Correct size of operand array.
* Fix a potential illegal array access in the D30V disassembler.Nick Clifton2019-10-292-1/+9
| | | | | * d30v-dis.c (print_insn): Check that operand index is valid before attempting to access the operands array.
* Prevent a left shift by a negative value when disassembling IA64 binaries.Nick Clifton2019-10-292-3/+11
| | | | | * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when locating the bit to be tested.
* Fix array overruns in the S12Z disassembler.Nick Clifton2019-10-293-16/+56
| | | | | | | * s12z-dis.c (opr_emit_disassembly): Check for illegal register values. (shift_size_table): Use a fixed size defined as S12Z_N_SIZES. (print_insn_s12z): Check for illegal size values.
* Fix potentially illegal shift and assign operation in CSKY disassembler.Nick Clifton2019-10-282-2/+7
| | | | | * csky-dis.c (csky_chars_to_number): Check for a negative count. Use an unsigned integer to construct the return value.
* Fix buffer overrun in TIC30 disassembler.Nick Clifton2019-10-282-7/+27
| | | | | | | | | | * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of operand buffer. Set value to 15 not 13. (get_register_operand): Use OPERAND_BUFFER_LEN. (get_indirect_operand): Likewise. (print_two_operand): Likewise. (print_three_operand): Likewise. (print_oar_insn): Likewise.
* Stop potential illegal memory access in the NS32K disassembler.Nick Clifton2019-10-282-1/+17
| | | | | | | | * ns32k-dis.c (bit_extract): Add sanitiy check of parameters. (bit_extract_simple): Likewise. (bit_copy): Likewise. (pirnt_insn_ns32k): Ensure that uninitialised elements in the index_offset array are not accessed.
* Prevent an illegal memory access in the xgate disassembler.Nick Clifton2019-10-282-3/+8
| | | | | * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA operand.
* Fix potential undefined behaviour in the RX disassembler.Nick Clifton2019-10-252-1/+6
| | | | | * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct access to opcodes.op array element.
* Fix typo in RX disassembler error messages.Nick Clifton2019-10-232-10/+19
| | | | | | | | | * rx-dis.c (get_register_name): Fix spelling typo in error message. (get_condition_name, get_flag_name, get_double_register_name) (get_double_register_high_name, get_double_register_low_name) (get_double_control_register_name, get_double_condition_name) (get_opsize_name, get_size_name): Likewise.
* Prevent more potential illegal memory accesses in the RX disassembler.Nick Clifton2019-10-222-16/+41
| | | | | | | * rx-dis.c (get_size_name): New function. Provides safe access to name array. (get_opsize_name): Likewise. (print_insn_rx): Use the accessor functions.
* Fix potential illegal memory access when disassembling corrupt RX binaries.Nick Clifton2019-10-162-15/+92
| | | | | | | | | | opcodes * rx-dis.c (get_register_name): New function. Provides safe access to name array. (get_condition_name, get_flag_name, get_double_register_name) (get_double_register_high_name, get_double_register_low_name) (get_double_control_register_name, get_double_condition_name): Likewise. (print_insn_rx): Use the accessor functions.
* Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton2019-10-092-0/+8
| | | | | | | | | PR 25041 opcodes * avr-dis.c (avr_operand): Fix construction of address for lds/sts instructions. gas * testsuite/gas/avr/pr25041.s: New test. * testsuite/gas/avr/pr25041.d: New test driver.
* S/390: Add support for z15 as CPU name.Andreas Krebbel2019-10-081-1/+2
| | | | | | | | | | | | | | | | | | | | | So far z15 was identified as arch13. After the machine has been announced we can now add the real name. gas/ChangeLog: 2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): Add z15 as alternate CPU name. * doc/as.texi: Add z15 to CPU string list. * doc/c-s390.texi: Likewise. opcodes/ChangeLog: 2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Enable z15 as CPU string in the opcode table.
* x86/Intel: correct MOVSD and CMPSD handlingJan Beulich2019-10-073-12/+18
| | | | | | | First and foremost the EsSeg attribute was misplaced for CMPSD. Then both it and MOVSD were lacking Dword on both of their operands. Finally string insns with multiple operands and requiring use of ES: had the wrong operand number reported in the diagnostic.