diff options
Diffstat (limited to '0037-x86-spec-ctrl-Enumeration-for-PBRSB_NO.patch')
| -rw-r--r-- | 0037-x86-spec-ctrl-Enumeration-for-PBRSB_NO.patch | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/0037-x86-spec-ctrl-Enumeration-for-PBRSB_NO.patch b/0037-x86-spec-ctrl-Enumeration-for-PBRSB_NO.patch new file mode 100644 index 0000000..d27766b --- /dev/null +++ b/0037-x86-spec-ctrl-Enumeration-for-PBRSB_NO.patch @@ -0,0 +1,67 @@ +From fba0c22e79922085c46527eb1391123aadfb24d1 Mon Sep 17 00:00:00 2001 +From: Andrew Cooper <andrew.cooper3@citrix.com> +Date: Mon, 15 Aug 2022 15:42:31 +0200 +Subject: [PATCH 37/67] x86/spec-ctrl: Enumeration for PBRSB_NO + +The PBRSB_NO bit indicates that the CPU is not vulnerable to the Post-Barrier +RSB speculative vulnerability. + +Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> +Reviewed-by: Jan Beulich <jbeulich@suse.com> +master commit: b874e47eb13feb75be3ee7b5dc4ae9c97d80d774 +master date: 2022-08-11 16:19:50 +0100 +--- + xen/arch/x86/msr.c | 2 +- + xen/arch/x86/spec_ctrl.c | 3 ++- + xen/include/asm-x86/msr-index.h | 1 + + 3 files changed, 4 insertions(+), 2 deletions(-) + +diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c +index aa9face9aad3..9bced8d36caa 100644 +--- a/xen/arch/x86/msr.c ++++ b/xen/arch/x86/msr.c +@@ -148,7 +148,7 @@ int init_domain_msr_policy(struct domain *d) + ARCH_CAPS_SSB_NO | ARCH_CAPS_MDS_NO | ARCH_CAPS_IF_PSCHANGE_MC_NO | + ARCH_CAPS_TAA_NO | ARCH_CAPS_SBDR_SSDP_NO | ARCH_CAPS_FBSDP_NO | + ARCH_CAPS_PSDP_NO | ARCH_CAPS_FB_CLEAR | ARCH_CAPS_RRSBA | +- ARCH_CAPS_BHI_NO); ++ ARCH_CAPS_BHI_NO | ARCH_CAPS_PBRSB_NO); + } + + d->arch.msr = mp; +diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c +index ac73806eacd8..3ff602bd0281 100644 +--- a/xen/arch/x86/spec_ctrl.c ++++ b/xen/arch/x86/spec_ctrl.c +@@ -419,7 +419,7 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps) + * Hardware read-only information, stating immunity to certain issues, or + * suggestions of which mitigation to use. + */ +- printk(" Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", ++ printk(" Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", + (caps & ARCH_CAPS_RDCL_NO) ? " RDCL_NO" : "", + (caps & ARCH_CAPS_IBRS_ALL) ? " IBRS_ALL" : "", + (caps & ARCH_CAPS_RSBA) ? " RSBA" : "", +@@ -431,6 +431,7 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps) + (caps & ARCH_CAPS_SBDR_SSDP_NO) ? " SBDR_SSDP_NO" : "", + (caps & ARCH_CAPS_FBSDP_NO) ? " FBSDP_NO" : "", + (caps & ARCH_CAPS_PSDP_NO) ? " PSDP_NO" : "", ++ (caps & ARCH_CAPS_PBRSB_NO) ? " PBRSB_NO" : "", + (e8b & cpufeat_mask(X86_FEATURE_IBRS_ALWAYS)) ? " IBRS_ALWAYS" : "", + (e8b & cpufeat_mask(X86_FEATURE_STIBP_ALWAYS)) ? " STIBP_ALWAYS" : "", + (e8b & cpufeat_mask(X86_FEATURE_IBRS_FAST)) ? " IBRS_FAST" : "", +diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h +index 49ca1f1845e6..5a830f76a8d4 100644 +--- a/xen/include/asm-x86/msr-index.h ++++ b/xen/include/asm-x86/msr-index.h +@@ -66,6 +66,7 @@ + #define ARCH_CAPS_FB_CLEAR_CTRL (_AC(1, ULL) << 18) + #define ARCH_CAPS_RRSBA (_AC(1, ULL) << 19) + #define ARCH_CAPS_BHI_NO (_AC(1, ULL) << 20) ++#define ARCH_CAPS_PBRSB_NO (_AC(1, ULL) << 24) + + #define MSR_FLUSH_CMD 0x0000010b + #define FLUSH_CMD_L1D (_AC(1, ULL) << 0) +-- +2.37.3 + |